Every Cheap Token Still Has a Physical Bill

Software deflation creates physical inflation.

The Two Trend Lines

TVC rests on two trend lines. Both are independently observable. Both are monitored daily.

Trend Line 1 — Cost per output token declining. Claude 3 Haiku output dropped over 80% year-over-year in late 2024.³ The Anthropic / OpenAI / Google composite basket fell more than 30% across 2024–2025. Gemini Flash crossed below $0.10 per million output tokens. The mechanism is hardware: each accelerator generation delivers more inference per watt, and the gain passes into pricing.⁴

Counter: hyperscaler enterprise tiers are rate-limited and contracted, so list-price decline overstates the actual buyer experience. The disclosed enterprise ARR figures are net of those caps and still triple-digit. The compounding lives in the volume.

Trend Line 2 — Utility per token rising. Cursor crossed $500M ARR in late 2024, exceeded $1B in November 2025, and reached over $2B by Q1 2026⁵ — a roughly 4× expansion in 14 months. GitHub Copilot Enterprise disclosed 77,000 organizations at $2B+ ARR-equivalent.⁶ Glean, Harvey, and Cognition all crossed triple-digit YoY growth.

Counter: reasoning models burn 10–100× more tokens per task. Utility per token may fall, but utility per task rises and tokens per task rise with it. Both effects increase the load on the physical stack.

This is not a point forecast. It is a mechanism estimate. A 50% cost decline, 3× adoption, and multi-fold tokens-per-task growth do not produce linear 1.5× demand. After rate limits, budget constraints, and deployment friction, the base case still points to multi-fold inference volume growth. We use ~6× as the monitored mechanism estimate.

Cost falls 50%, adoption rises 3×, reasoning burns more tokens per task. The “6× — not 1.5×” reframe is the entire mechanism.

Why This Re-rates the Physical Stack

Every additional token of inference is a physical event. Electrons, photons, chemicals, manufactured hardware. None scale automatically with software demand.

Large power transformers above 500 MVA carry 36–48 month lead times.⁷ CoWoS capacity expansion takes four years.⁸ HBM is allocated through 2026 with 2027 pre-sold.⁹ Software adoption curves are weeks. Capacity expansion curves are years. The gap is the trade. Chain Two Layers Deeper extends the same mechanism across the full eight-layer surface.

Four buckets, eight layers

The eight layers do not bind at the same time or behave the same way under stress. They sort into four buckets:

• Already binding. L1 Compute, L2 HBM, L4 Advanced Packaging. Allocations are sold through 2026. 2027 is substantially pre-committed.
• Tightening into 2026–2027. L5 Chemistry, L6 Power, L7 Cooling. Where second-order beneficiaries live, and where mispricing concentrates.
• Paid in any scenario. L8 EDA. Royalty on complexity. Wins whether NVIDIA dominates or hyperscaler ASIC programs grow.
• Watch layer, not binding layer. L3 Storage. Becomes binding on a 2027 roadmap if HBF endorsement materializes; not yet load-bearing on the thesis.

Where the ForcedAlpha edge concentrates

The ForcedAlpha edge is highest where the supplier list is narrow, the qualification cycle is long, and the market still categorizes the company outside AI.

The body sections below run through each layer in order. The market has re-rated the visible AI layer at the top — NVIDIA, TSMC. It has not yet re-rated all of the physical receivers below it.

Why this re-rates now

1. Frontier model prices have fallen enough to stimulate real usage. The Anthropic / OpenAI / Google composite basket fell more than 30% YoY across 2024–25, and Gemini Flash crossed below $0.10 per million output tokens.³
2. Agentic workflows are moving from demos to enterprise deployment. Cursor went from $500M to over $2B ARR in 14 months. GitHub Copilot disclosed 77,000 enterprise organizations.⁵⁶
3. Reasoning models consume far more tokens per task. Tokens-per-task increases of 10–100× change the unit economics of every customer-facing agent.
4. HBM and CoWoS are already sold through 2026. 2027 is substantially pre-committed across SK Hynix, Micron, and Samsung HBM lines and TSMC CoWoS capacity.⁹
5. Power and cooling bottlenecks are now visible in datacenter buildouts. Large power transformers above 500 MVA carry 36–48 month lead times; medium-voltage switchgear runs 18–24 months.⁷
6. Captive ASICs do not reduce the physical stack — they broaden it. Google TPU, AWS Trainium, Microsoft Maia, and Meta MTIA all ride TSMC, HBM, ABF, power, and cooling. Bear A pivots the trade surface above the physics; the physics stays binding.
7. The market has re-rated the visible AI layer but not all of the physical receivers below it. NVIDIA and TSMC are priced. The eight-layer surface beneath is not uniformly priced.

Position Implication, Plain

The eight layers do not produce one trade. They produce a portfolio with a sequenced binding-time schedule. The structural lean, before any Pro-tier convergence scoring or live cascade indicator, runs as follows:

Three types of alpha in this thesis

The eight layers split into three trade types, each with a different edge and a different spread.

NVIDIA is the visible trade. The forced trade may sit two to six layers beneath it.

Layer 1: Compute Accelerators

Compute is where token economics originate. NVIDIA dominates merchant inference silicon. TSMC manufactures almost all leading-edge logic at 3nm and 5nm. Broadcom and Marvell co-design Google's TPU v6e Trillium and Microsoft's Maia 100.

The binding constraint is not dies. It is CoWoS — TSMC's advanced packaging — which assembles GPU + HBM into a finished accelerator. TSMC operates CoWoS at production scale with no merchant alternative at equivalent advanced-node capacity currently visible.⁸ Performance per watt improves ~2.5× per accelerator generation per MLPerf data,⁴ which is what drives the cost-per-token decline at Trend Line 1.

Networking is part of Layer 1. Marvell's electro-optic DSPs ship 800G and 1.6T pluggable optics; Broadcom's Tomahawk 5 and 6 dominate hyperscaler Ethernet fabrics; Coherent (COHR) and Lumentum (LITE) supply the EMLs that drive PAM4 datacenter optics. Co-packaged optics (CPO) — the next bandwidth-density step — is in qualification at Broadcom, Marvell, TSMC, and Coherent in 2026. Every token traversed in an inference cluster crosses the fabric.

Layer 2: High-Bandwidth Memory

HBM is fully allocated through 2026. 2027 is substantially pre-committed. SK Hynix holds ~50% share, Micron ~25%, Samsung ~15%. Each H100 GPU requires six HBM3 stacks; each Blackwell B100 requires eight HBM3E.

The MR-MUF underfill chemistry that lets HBM stack at all runs through Ajinomoto Fine-Techno and Resonac (formerly Showa Denko) with no third qualified supplier visible.¹⁰

HBM4 is shipping samples. SK Hynix holds ~70% of NVIDIA’s Rubin allocation; Samsung ~30%. Micron led HBM3E and is now locked out pending qualification. A Micron requalification before late 2026 is cascade-tracked. If Micron does not regain Rubin allocation, concentration at SK Hynix increases further. JEDEC base specs and Rubin supplier specs differ (see appendix).⁹

HBM is not DDR5 RDIMM. HBM is allocated, multi-year contracted, and supply-bound — there is no spot market. DDR5 RDIMM is commodity-cyclical. The TVC thesis is HBM-specific. Generalist memory exposure to Micron, SK Hynix, or Samsung captures both, and the DDR5 cyclicality can mask the HBM allocation picture in any given quarter. → see Appendix: HBM4 specifications.

Layer 3: Enterprise NAND Storage

Layer 3 is emerging, not binding. Today’s binding inference constraints sit at L1, L2, L4, L5, L6, and L7. Enterprise NAND becomes binding on a 2027 horizon through two mechanisms: persistent agent state across sessions, and KV-cache offloading at long-context inference scale.

Both are pre-production at frontier vendors today. The HBF (High-Bandwidth Flash) standard is under development at OCP (Open Compute Project), co-developed by SK Hynix and SanDisk. If hyperscaler endorsement materializes in 2026–2027, HBF would structurally bind NAND into the inference memory hierarchy as a new product category. The cascade tracks SanDisk and SK Hynix HBF disclosures; ADEIA (ADEA) is gated on hyperscaler endorsement.

Layer 4: Advanced Packaging

Three packaging materials gate AI accelerator output. The silicon interposer for CoWoS (Chip on Wafer on Substrate) is manufactured at TSMC at production scale, with no merchant alternative at equivalent advanced-node capacity currently visible. ABF (Ajinomoto Build-up Film) is the dielectric layer in advanced organic substrates produced by Ibiden and Unimicron. It has no production-scale qualified alternative visible.¹¹ The MR-MUF underfill chemistry (described at L2) is the third.

For HBM4 hybrid bonders, BESI (BE Semiconductor Industries) holds an estimated 75–85% share, with Applied Materials (AMAT) as the secondary option.

Layer 5: Specialty Chemistry

Layer 5 is the most structurally concentrated layer. Specialty chemicals at advanced nodes — photoresists, etchants, ALD precursors, ultra-pure gases, underfill — come from a small set of mostly Japanese and Korean producers with 12–36 month qualification cycles.

EUV photoresist is dominated by JSR (privatized via JIC), Tokyo Ohka Kogyo, and Shin-Etsu Chemical — together ~85–90% of global share per Techcet.¹² Sumitomo Chemical holds the remaining 10–15%. Ultra-high-purity hydrofluoric acid (HF) is supplied by Stella Chemifa and Kanto Denka; Soulbrain (036830.KQ) is the sole Korean-domiciled merchant-scale HF supplier for Samsung and SK Hynix memory — load-bearing for procurement chains with geographic qualification requirements.

ALD precursors for high-k dielectrics (HfO₂, ZrO₂) come from Merck KGaA (post-Versum), ADEKA (4401.T), and DNF (092070.KQ). CMP slurries — used to polish each wafer layer flat between patterning steps — are a separate concentrated chokepoint: Resonac is the global leader in tungsten and copper CMP at advanced nodes, with CMC Materials (acquired by Entegris in 2022) secondary. Each successive node generation requires more CMP steps; demand scales super-linearly with node-count progression.

Resonac sits at two structurally distinct chokepoints in the AI fab cascade: CMP slurries here and MR-MUF underfill at Layer 2. Industrial gases (Linde, Air Products) operate on-site plants at TSMC, Samsung, and Intel — quasi-captive once established. → see Appendix: Specialty chemistry mechanics.

Layer 6: Electrical Infrastructure

Every AI datacenter is, structurally, a power plant with servers attached. Large power transformers, medium-voltage switchgear, UPS, PDUs — lead times in years, not months. The manufacturing base is fewer than ten companies globally.

LPTs above 500 MVA carry 36–48 month lead times globally as of 2026.⁷ The base is concentrated in South Korea (HD Hyundai Electric, Hyosung Heavy), Germany (ABB, Siemens Energy), and a declining US presence. US datacenter electricity consumption is projected at 8–12% of total grid load by 2030 per EPRI estimates, up from ~4% in 2022.¹³

Medium-voltage switchgear at Eaton and similar suppliers carries 18–24 month lead times. Powell Industries (POWL), specialized in MV switchgear with disclosed multi-year backlogs, is the cleanest pure-play expression of the bottleneck. Schneider Electric acquired Motivair in October 2024, becoming the primary vertically integrated power-plus-cooling supplier alongside Eaton and Vertiv.

The grid itself is now formally rationed. PJM Interconnection — the largest US RTO, serving 65M people across 13 states + DC — held two consecutive Base Residual Auctions at the FERC-approved price cap. The 2027/28 BRA was the first in PJM history (since 2007) to fail to procure enough capacity to meet the reliability target, falling 6,623 MW short. PJM CEO David Mills, in a May 8 2026 stakeholder letter, named the situation directly: "an era of scarcity," "structurally different from prior periods of tightness," "the current situation is not tenable." The cost of a marginal token is no longer just the chip layer — it is increasingly the grid, where the resolution path runs through GOES (Cleveland-Cliffs Butler is the sole US merchant producer), large power transformers (HD Hyundai, Hyosung), and either nuclear restarts (years) or behind-the-meter gas turbines (24–36 month lead times). The substrate cost has migrated upstream of silicon. PJM letter · 2027/28 BRA results

Layer 7: Liquid Cooling

Chip power density has crossed the threshold where air cooling no longer works for AI racks. The NVIDIA GB200 NVL72 — the reference rack for Blackwell — requires direct liquid cooling. Liquid cooling is now mandatory infrastructure, not an upgrade.

The supply surface is striking for how concentrated it is in private companies. Boyd (Goldman Sachs PE), CoolIT (KKR 2023), LiquidStack (Carrier Global), and Submer (BlackRock-led 2024) are all private. Motivair was acquired by Schneider Electric in October 2024, removing the last independent mid-size public liquid cooling specialist. Asetek (ASTK.OL, Oslo Bors) is publicly listed but is predominantly a consumer all-in-one (AIO) liquid-cooler vendor — its datacenter line is small revenue share, float is sub-$100M.

There is no good US/Europe-listed mid-cap pure-play on datacenter liquid cooling. Vertiv (VRT) provides the broadest publicly accessible exposure at scale. CDU lead times are disclosed at 6–12 months by Vertiv. PFAS regulation — EPA and ECHA actions expected in 2026 — could force reformulation of dielectric cooling fluids in immersion systems, adding supply disruption to that segment.

Layer 8: EDA — Royalty on Silicon Fragmentation

Every captive ASIC — Google TPU, AWS Trainium, Microsoft Maia, Meta MTIA — runs through Synopsys and Cadence. EDA is the design-layer chokepoint for the captive-silicon wave Bear A describes. As captive share rises, EDA royalty per tape-out rises with it. EDA gets paid first whether the buyer is NVIDIA, Google, AWS, or Microsoft.

Synopsys and Cadence together hold ~80–90% of advanced-node EDA. Synopsys closed the Ansys acquisition in July 2025, with Q1 2026 the first integrated quarter — expanding the standard digital flow into system-level simulation for chiplet, 2.5D, and 3D advanced-package designs. Cadence’s competitive response is its generative-AI design suite. Both vendors are pricing AI-augmented tooling as premium-tier additions, expanding revenue per seat at hyperscaler customers.

ARM Holdings holds the same near-monopoly at the instruction-set layer. Google Axion, AWS Graviton, Microsoft Cobalt, Ampere Altra, and NVIDIA Grace all license ARM v9-A. Hyperscaler ARM royalty is the layer beneath the captive-silicon wave: every captive ASIC tape-out is also an ARM royalty event. Even if Broadcom and Marvell capture the merchant ASIC co-design, ARM still gets paid on every die.

The Chinese counterweight runs at low-single-digit global share. The named producers are Empyrean (301269.SZ), Primarius (688206.SH), and Semitronix (688053.SH). China cannot tape out 7nm-and-below today without Synopsys or Cadence. Even if 2027–2028 brings a Chinese advanced-node flow, the Western captive-silicon royalty stream stays locked to Synopsys, Cadence, and ARM. Tape-out volume scales with captive-silicon ramp; ramp scales with inference load — TVC, end-to-end. → see Appendix: EDA market structure.

The Three Bear Cases

Some bear cases kill the trade. Others only move the bottleneck. The thesis has three distinct stress modes. Bear A is a pivot in the trade surface. Bear B is a falsifier of the demand mechanism. Bear C compresses the bottleneck premium without falsifying the thesis. They behave differently and should be managed differently.

What We're Watching

How to Read the Cascade

Each casefile is backed by a machine-verifiable hypothesis registry — a structured way of tracking whether the thesis claims remain true over time.

This is why the dependency graph matters. AI demand does not hit one company. It propagates through a stack. ForcedAlpha maps the propagation.

Appendix: Technical Depth

Detail that supports the body claims but is not required to read in flow. For primary sources, see the footnotes.

HBM4 Specifications

The published JEDEC HBM4 base specification is 8 Gb/s pin-speed, delivering ~2.0 TB/s per stack across the 2,048-bit interface. NVIDIA's Rubin-targeted supplier specifications run at 13 Gb/s pin-speed, delivering ~2.6 TB/s per stack — an over-spec relative to the JEDEC base, negotiated bilaterally with SK Hynix and Samsung.⁹ The bandwidth uplift is what drives the Vera Rubin platform's per-GPU throughput target. HBM4 is delivered as a stack of 12-high or 16-high DRAM dies connected through TSVs (through-silicon vias — microscopic copper pillars that carry electrical signals through silicon). Each H100 GPU requires six HBM3 stacks; each Blackwell B100 requires eight HBM3E.

EDA Market Structure

Synopsys-Ansys integration adds multiphysics simulation to the standard digital and custom-silicon flow: thermal, electromagnetic, and structural. Captive-silicon programs increasingly require this for chiplet, 2.5D, and 3D advanced-package designs. Cadence's competitive response is Cerebrus and the broader JedAI generative-AI design suite, which uses reinforcement-learning-style search across the place-and-route and optimisation steps to compress design cycles. ARM v9-A is the licensed core architecture in virtually every hyperscaler-built ASIC at advanced nodes. The Chinese EDA position sits at low single-digit global share but is growing inside Chinese fab and design-house workflows under explicit state industrial-policy support. The named producers are Empyrean Technology, Primarius Technologies, and Semitronix. China cannot tape out 7nm-and-below logic without Synopsys or Cadence today; whether 2027–2028 produces a meaningful Chinese flow at advanced nodes is the strategic question.

Specialty Chemistry Mechanics

CMP (Chemical-Mechanical Planarization) slurries are abrasive-chemical mixtures used to polish each layer of a wafer flat between patterning steps. Resonac's CMP leadership traces to the Showa Denko + Hitachi Chemical merger and the Sigma-Aldrich-derived advanced-material lines integrated into the combined entity. Merck KGaA's electronics business is top-3 in semiconductor materials after the Versum Materials acquisition in 2019. ALD (Atomic Layer Deposition) deposits thin films one atomic layer at a time and is the standard for high-k dielectrics like HfO₂ and ZrO₂ used in advanced DRAM cells and HBM stacking.

MR-MUF Chemistry

MR-MUF (Mass Reflow Molded Underfill) is a bromide-based epoxy material that fills the gaps between stacked HBM dies during the reflow step, providing thermal and mechanical stability at production scale. It runs through Ajinomoto Fine-Techno and Resonac (formerly Showa Denko) with no third qualified supplier visible at any HBM producer.¹⁰ The chemistry is what makes vertical HBM stacking manufacturable at all; without MR-MUF, HBM as a product category does not exist.